标签：示例 comp component analysis uvm trans port
此例显示将同一analysis port 连接到多个组件的analysis imp port。
TesetBench 组件
————————————————————–
Name Type
————————————————————–
uvm_test_top basic_test
env environment
comp_a component_a
analysis_port uvm_analysis_port
comp_b component_b
analysis_imp uvm_analysis_imp
comp_c component_c
analysis_imp uvm_analysis_imp
————————————————————–
在 comp_a 中实现 analysis port
class component_a extends uvm_component;
transaction trans;
uvm_analysis_port#(transaction) analysis_port;
`uvm_component_utils(component_a)
//---------------------------------------
// Constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
analysis_port = new("analysis_port", this);
endfunction : new
//---------------------------------------
// run_phase
//---------------------------------------
virtual task run_phase(uvm_phase phase);
phase.raise_objection(this);
trans = transaction::type_id::create("trans", this);
void'(trans.randomize());
`uvm_info(get_type_name(),$sformatf(" tranaction randomized"),UVM_LOW)
`uvm_info(get_type_name(),$sformatf(" Printing trans, \n %s",trans.sprint()),UVM_LOW)
`uvm_info(get_type_name(),$sformatf(" Before calling port write method"),UVM_LOW)
analysis_port.write(trans);
`uvm_info(get_type_name(),$sformatf(" After calling port write method"),UVM_LOW)
phase.drop_objection(this);
endtask : run_phase
endclass : component_a在 comp_b 中实现analysis imp_port
class component_b extends uvm_component;
transaction trans;
uvm_analysis_imp#(transaction,component_b) analysis_imp;
`uvm_component_utils(component_b)
//---------------------------------------
// Constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
analysis_imp = new("analysis_imp", this);
endfunction : new
//---------------------------------------
// Imp port put method
//---------------------------------------
virtual function void write(transaction trans);
`uvm_info(get_type_name(),$sformatf(" Inside write method. Recived trans On Analysis Imp Port"),UVM_LOW)
`uvm_info(get_type_name(),$sformatf(" Printing trans, \n %s",trans.sprint()),UVM_LOW)
endfunction
endclass : component_b在 comp_c 中实现analysis imp_port
class component_c extends uvm_component;
transaction trans;
uvm_analysis_imp#(transaction,component_c) analysis_imp;
`uvm_component_utils(component_c)
//---------------------------------------
// Constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
analysis_imp = new("analysis_imp", this);
endfunction : new
//---------------------------------------
// Imp port put method
//---------------------------------------
virtual function void write(transaction trans);
`uvm_info(get_type_name(),$sformatf(" Inside write method. Recived trans On Analysis Imp Port"),UVM_LOW)
`uvm_info(get_type_name(),$sformatf(" Printing trans, \n %s",trans.sprint()),UVM_LOW)
endfunction
endclass : component_c在 env 中连接analysis port和analysis imp_ports
`include "transaction.sv"
`include "component_a.sv"
`include "component_b.sv"
`include "component_c.sv"
class environment extends uvm_env;
//---------------------------------------
// Components Instantiation
//---------------------------------------
component_a comp_a;
component_b comp_b;
component_c comp_c;
`uvm_component_utils(environment)
//---------------------------------------
// Constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction : new
//---------------------------------------
// build_phase - Create the components
//---------------------------------------
function void build_phase(uvm_phase phase);
super.build_phase(phase);
comp_a = component_a::type_id::create("comp_a", this);
comp_b = component_b::type_id::create("comp_b", this);
comp_c = component_c::type_id::create("comp_c", this);
endfunction : build_phase
//---------------------------------------
// Connect_phase
//---------------------------------------
function void connect_phase(uvm_phase phase);
comp_a.analysis_port.connect(comp_b.analysis_imp);
comp_a.analysis_port.connect(comp_c.analysis_imp);
endfunction : connect_phase
endclass : environment仿真结果：
UVM_INFO @ 0: reporter [RNTST] Running test basic_test...
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
uvm_test_top basic_test - @1817
env environment - @1884
comp_a component_a - @1916
analysis_port uvm_analysis_port - @1967
comp_b component_b - @2000
analysis_imp uvm_analysis_imp - @2050
comp_c component_c - @2081
analysis_imp uvm_analysis_imp - @2131
---------------------------------------------------
UVM_INFO component_a.sv(29) @ 0: uvm_test_top.env.comp_a [component_a] tranaction randomized
UVM_INFO component_a.sv(30) @ 0: uvm_test_top.env.comp_a [component_a] Printing trans,
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @2185
addr integral 4 'h3
wr_rd integral 1 'h0
wdata integral 8 'h33
---------------------------------
UVM_INFO component_a.sv(32) @ 0: uvm_test_top.env.comp_a [component_a] Before calling port write method
UVM_INFO component_b.sv(24) @ 0: uvm_test_top.env.comp_b [component_b] Inside write method. Recived trans On Analysis Imp Port
UVM_INFO component_b.sv(25) @ 0: uvm_test_top.env.comp_b [component_b] Printing trans,
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @2185
addr integral 4 'h3
wr_rd integral 1 'h0
wdata integral 8 'h33
---------------------------------
UVM_INFO component_c.sv(24) @ 0: uvm_test_top.env.comp_c [component_c] Inside write method. Recived trans On Analysis Imp Port
UVM_INFO component_c.sv(25) @ 0: uvm_test_top.env.comp_c [component_c] Printing trans,
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @2185
addr integral 4 'h3
wr_rd integral 1 'h0
wdata integral 8 'h33
---------------------------------
UVM_INFO component_a.sv(34) @ 0: uvm_test_top.env.comp_a [component_a] After calling port write method
UVM_INFO /xcelium20.09/tools//methodology/UVM/CDNS-1.2/sv/src/base/uvm_objection.svh(1271) @ 0: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_INFO /xcelium20.09/tools//methodology/UVM/CDNS-1.2/sv/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER]
标签：示例,comp,component,analysis,uvm,trans,port 来源： https://www.cnblogs.com/fuqiangblog/p/16683404.html
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