标签：11 示例 get component uvm phase trans port TLM
TLM FIFO 为两个独立运行的进程之间的事务提供存储服务。
- FIFO可以用作生产者和消费者之间的缓冲区
- TLM FIFO 由 put 和 get 方法组成
- Producer port连接到 FIFO 的 put_export
- Consumer port连接到FIFO的get_export
TLM TesetBench 组件
————————————————————–
Name Type
————————————————————–
uvm_test_top basic_test
env environment
comp_a component_a
trans_out uvm_blocking_put_port
comp_b component_b
trans_in uvm_blocking_get_port
fifo_ab uvm_tlm_fifo #(T)
get_ap uvm_analysis_port
get_peek_export uvm_get_peek_imp
put_ap uvm_analysis_port
put_export uvm_put_imp
————————————————————–
在 comp_a 中实现port
class component_a extends uvm_component;
transaction trans;
uvm_blocking_put_port#(transaction) trans_out;
`uvm_component_utils(component_a)
//---------------------------------------
// Constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
trans_out = new("trans_out", this);
endfunction : new
//---------------------------------------
// run_phase
//---------------------------------------
virtual task run_phase(uvm_phase phase);
phase.raise_objection(this);
trans = transaction::type_id::create("trans", this);
void'(trans.randomize());
`uvm_info(get_type_name(),$sformatf(" tranaction randomized"),UVM_LOW)
`uvm_info(get_type_name(),$sformatf(" Printing trans, \n %s",trans.sprint()),UVM_LOW)
`uvm_info(get_type_name(),$sformatf(" Before calling port put method"),UVM_LOW)
trans_out.put(trans);
`uvm_info(get_type_name(),$sformatf(" After calling port put method"),UVM_LOW)
phase.drop_objection(this);
endtask : run_phase
endclass : component_a在 comp_b 中实现port
class component_b extends uvm_component;
transaction trans;
uvm_blocking_get_port#(transaction) trans_in;
`uvm_component_utils(component_b)
//---------------------------------------
// Constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
trans_in = new("trans_in", this);
endfunction : new
//---------------------------------------
// run_phase
//---------------------------------------
virtual task run_phase(uvm_phase phase);
phase.raise_objection(this);
`uvm_info(get_type_name(),$sformatf(" Before calling port get method"),UVM_LOW)
trans_in.get(trans);
`uvm_info(get_type_name(),$sformatf(" After calling port get method"),UVM_LOW)
`uvm_info(get_type_name(),$sformatf(" Printing trans, \n %s",trans.sprint()),UVM_LOW)
phase.drop_objection(this);
endtask : run_phase
endclass : component_b在env中实现 TLM FIFO
`include "transaction.sv"
`include "component_a.sv"
`include "component_b.sv"
class environment extends uvm_env;
//---------------------------------------
// Components Instantiation
//---------------------------------------
component_a comp_a;
component_b comp_b;
uvm_tlm_fifo #(transaction) fifo_ab;
`uvm_component_utils(environment)
//---------------------------------------
// Constructor
//---------------------------------------
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction : new
//---------------------------------------
// build_phase - Create the components
//---------------------------------------
function void build_phase(uvm_phase phase);
super.build_phase(phase);
comp_a = component_a::type_id::create("comp_a", this);
comp_b = component_b::type_id::create("comp_b", this);
fifo_ab = new("fifo_ab", this);
endfunction : build_phase
//---------------------------------------
// Connect_phase
//---------------------------------------
function void connect_phase(uvm_phase phase);
comp_a.trans_out.connect(fifo_ab.put_export);
comp_b.trans_in.connect(fifo_ab.get_export);
endfunction : connect_phase
endclass : environment仿真结果：
UVM_INFO @ 0: reporter [RNTST] Running test basic_test...
---------------------------------------------------------
Name Type Size Value
---------------------------------------------------------
uvm_test_top basic_test - @1815
env environment - @1882
comp_a component_a - @1914
trans_out uvm_blocking_put_port - @1965
comp_b component_b - @1998
trans_in uvm_blocking_get_port - @2048
fifo_ab uvm_tlm_fifo #(T) - @1999
get_ap uvm_analysis_port - @2278
get_peek_export uvm_get_peek_imp - @2178
put_ap uvm_analysis_port - @2228
put_export uvm_put_imp - @2128
---------------------------------------------------------
UVM_INFO component_b.sv(26) @ 0: uvm_test_top.env.comp_b [component_b] Before calling port get method
UVM_INFO component_a.sv(29) @ 0: uvm_test_top.env.comp_a [component_a] tranaction randomized
UVM_INFO component_a.sv(30) @ 0: uvm_test_top.env.comp_a [component_a] Printing trans,
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @1857
addr integral 4 'h3
wr_rd integral 1 'h0
wdata integral 8 'h33
---------------------------------
UVM_INFO component_a.sv(32) @ 0: uvm_test_top.env.comp_a [component_a] Before calling port put method
UVM_INFO component_a.sv(34) @ 0: uvm_test_top.env.comp_a [component_a] After calling port put method
UVM_INFO component_b.sv(28) @ 0: uvm_test_top.env.comp_b [component_b] After calling port get method
UVM_INFO component_b.sv(29) @ 0: uvm_test_top.env.comp_b [component_b] Printing trans,
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @1857
addr integral 4 'h3
wr_rd integral 1 'h0
wdata integral 8 'h33
---------------------------------
标签：11,示例,get,component,uvm,phase,trans,port,TLM 来源： https://www.cnblogs.com/fuqiangblog/p/16677864.html
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