ICode9

精准搜索请尝试: 精确搜索
首页 > 其他分享> 文章详细

TLM通信示例9:连接 TLM 非阻塞 get port

2022-09-10 17:05:17  阅读:363  来源: 互联网

标签:get comp 示例 component uvm phase trans TLM


这个例子展示了如何声明、创建和连接 TLM non-blocking get ports

TLM TesetBench 组件

———————————————————- 
Name                    Type 
———————————————————- 
uvm_test_top        basic_test 
env                    environment 
comp_a         component_a 
trans_out   uvm_nonblocking_get_imp 
comp_b         component_b 
trans_in     uvm_nonblocking_get_port 
———————————————————-

在 comp_b 中声明并创建 TLM Get Port

class component_b extends uvm_component;
  
  transaction trans;
  uvm_nonblocking_get_port#(transaction) trans_in;  

  `uvm_component_utils(component_b)
  
  //--------------------------------------- 
  // Constructor
  //---------------------------------------
  function new(string name, uvm_component parent);
    super.new(name, parent);
    trans_in = new("trans_in", this);
  endfunction : new 
  
  //---------------------------------------
  // run_phase 
  //---------------------------------------
  virtual task run_phase(uvm_phase phase);
    phase.raise_objection(this);

    `uvm_info(get_type_name(),$sformatf(" Requesting transaction."),UVM_LOW)
    
    `uvm_info(get_type_name(),$sformatf(" Before calling port get method"),UVM_LOW)
    
    if(trans_in.try_get(trans)) begin //{
      `uvm_info(get_type_name(),$sformatf(" recived transaction from get method"),UVM_LOW)
      `uvm_info(get_type_name(),$sformatf(" Printing trans, \n %s",trans.sprint()),UVM_LOW)
    end //} 
    else
      `uvm_info(get_type_name(),$sformatf(" Not recived transaction from get method"),UVM_LOW)
    
    `uvm_info(get_type_name(),$sformatf(" After  calling port get method"),UVM_LOW)

    
    phase.drop_objection(this);
  endtask : run_phase
  
endclass : component_b

try_get() 方法用于接收事务。 try_get() 方法在成功接收事物时返回“1”,否则返回“0”。

在 comp_a 中声明并创建 TLM Imp_port

class component_a extends uvm_component;
  
  uvm_nonblocking_get_imp#(transaction,component_a) trans_out; 
  
  `uvm_component_utils(component_a)
  
  //--------------------------------------- 
  // Constructor
  //---------------------------------------
  function new(string name, uvm_component parent);
    super.new(name, parent);
    trans_out = new("trans_out", this); 
  endfunction : new

  //---------------------------------------
  // Imp port try_get method
  //---------------------------------------
  virtual function bit try_get(output transaction trans);
    
    `uvm_info(get_type_name(),$sformatf(" Recived transaction imp port get request"),UVM_LOW)
    trans = transaction::type_id::create("trans", this);
    
    void'(trans.randomize());
    `uvm_info(get_type_name(),$sformatf(" tranaction randomized"),UVM_LOW)
    `uvm_info(get_type_name(),$sformatf(" Printing trans, \n %s",trans.sprint()),UVM_LOW)

    `uvm_info(get_type_name(),$sformatf(" Sendting trans packet"),UVM_LOW)
    
    return 1;
  endfunction   
  
  //---------------------------------------
  // Imp port can_get method
  //---------------------------------------
  virtual function bit can_get();

  endfunction
endclass : component_a

由于 port 是非阻塞的,try_get( )方法应该作为function而不是task来实现。

在 env 中连接 TLM port和 Imp port

`include "transaction.sv"
`include "component_a.sv"
`include "component_b.sv"

class environment extends uvm_env;
  
  //---------------------------------------
  // Components Instantiation
  //---------------------------------------
  component_a comp_a;
  component_b comp_b;
  
  `uvm_component_utils(environment)
  
  //--------------------------------------- 
  // Constructor
  //---------------------------------------
  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction : new

  //---------------------------------------
  // build_phase - Create the components
  //---------------------------------------
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);

    comp_a = component_a::type_id::create("comp_a", this);
    comp_b = component_b::type_id::create("comp_b", this);
  endfunction : build_phase
  
  //---------------------------------------
  // Connect_phase 
  //---------------------------------------
  function void connect_phase(uvm_phase phase);
    comp_b.trans_in.connect(comp_a.trans_out);
  endfunction : connect_phase
endclass : environment

 

仿真结果:

UVM_INFO @ 0: reporter [RNTST] Running test basic_test...
------------------------------------------------------
Name Type Size Value
------------------------------------------------------
uvm_test_top basic_test - @336
env environment - @349
comp_a component_a - @358
trans_out uvm_nonblocking_get_imp - @367
comp_b component_b - @377
trans_in uvm_nonblocking_get_port - @386
------------------------------------------------------
UVM_INFO component_b.sv(26) @ 0: uvm_test_top.env.comp_b [component_b] Requesting transaction.
UVM_INFO component_b.sv(28) @ 0: uvm_test_top.env.comp_b [component_b] Before calling port get method
UVM_INFO component_a.sv(24) @ 0: uvm_test_top.env.comp_a [component_a] Recived transaction imp port get request
UVM_INFO component_a.sv(28) @ 0: uvm_test_top.env.comp_a [component_a] tranaction randomized
UVM_INFO component_a.sv(29) @ 0: uvm_test_top.env.comp_a [component_a] Printing trans,
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @410
addr integral 4 'h4
wr_rd integral 1 'h0
wdata integral 8 'hd0
---------------------------------

UVM_INFO component_a.sv(31) @ 0: uvm_test_top.env.comp_a [component_a] Sendting trans packet
UVM_INFO component_b.sv(31) @ 0: uvm_test_top.env.comp_b [component_b] recived transaction from get method
UVM_INFO component_b.sv(32) @ 0: uvm_test_top.env.comp_b [component_b] Printing trans,
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @410
addr integral 4 'h4
wr_rd integral 1 'h0
wdata integral 8 'hd0
---------------------------------

UVM_INFO component_b.sv(37) @ 0: uvm_test_top.env.comp_b [component_b] After calling port get method
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_objection.svh(1276) @ 0: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 0: reporter [UVM/REPORT/SERVER]

 

标签:get,comp,示例,component,uvm,phase,trans,TLM
来源: https://www.cnblogs.com/fuqiangblog/p/16677317.html

本站声明: 1. iCode9 技术分享网(下文简称本站)提供的所有内容,仅供技术学习、探讨和分享;
2. 关于本站的所有留言、评论、转载及引用,纯属内容发起人的个人观点,与本站观点和立场无关;
3. 关于本站的所有言论和文字,纯属内容发起人的个人观点,与本站观点和立场无关;
4. 本站文章均是网友提供,不完全保证技术分享内容的完整性、准确性、时效性、风险性和版权归属;如您发现该文章侵犯了您的权益,可联系我们第一时间进行删除;
5. 本站为非盈利性的个人网站,所有内容不会用来进行牟利,也不会利用任何形式的广告来间接获益,纯粹是为了广大技术爱好者提供技术内容和技术思想的分享性交流网站。

专注分享技术,共同学习,共同进步。侵权联系[81616952@qq.com]

Copyright (C)ICode9.com, All Rights Reserved.

ICode9版权所有